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VHDL online training

VHDL



overview


VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

Advantages of VHDL:


The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.

prerequisties

  • Good working knowledge of digital hardware design

Duration

Online
  • It is a 20 days program and extends up to 2hrs each.
  • The format is 20% theory, 80% Hands-on.

Corporate
  • It is a 5 days program and extends up to 8hrs each.
  • The format is 20% theory, 80% Hands-on.
Classroom
    Private Classroom arranged on request and minimum attendies for batch is 4.

course content

  • CODE STRUCTURE
    • Library Declaration
    • Entity
    • Architecture
    • Configuration
  • DATA TYPES & OBJECTS IN VHDL
    • Variables
    • Constants
    • Signals
    • Delta Delay
    • Operators in VHDL
    • Shift Operator
    • Relational Operator
    • Arithmetic Operator
    • User-Defined Data Types
    • Pre-Defined Data Types
    • Arrays
    • Record
  • DATA FLOW MODELING
    • Keyword description of Dataflow Modeling.
    • When else statement.
    • With Select Statement
  • BEHAVIORAL MODELING
    • Process Keyword.
    • Conditional Statements
    • If else statement
    • Case statement
    • Loops in VHDL
    • For Loop
    • While Loop
    • No Iteration Scheme Loop
    • Sequential Circuits in Behavioral Modeling
    • Flip-Flops
    • Counters
    • Combinational Circuits in Behavioral Modeling
    • Decoder
    • Encoder
    • Multiplexer
    • Logic Gates
    • Attribute
    • Signal Attribute
    • Data Attribute
    • User-Defined Attribute
    • Package
    • Pre-defined Package
    • User-defined Package
    • Sub programs.
    • Function.
    • Local Function
    • Pre-defined Function
    • Procedure.
    • Local Procedure
    • Pre-defined Procedure
    • NULL Statement
    • NEXT Statement
    • EXIT Statement
  • STRUCTURAL MODELING
    • Benefits of Structural Modeling.
    • Components.
    • Component Interfacing
    • Port Mapping
  • FINITE STATE MACHINE
    • Introduction to FINITE STATE MACHINE (FSM)
    • Moore’s Machine
    • Mealy Machine.
    • Counters (MOD-3, MOD-5, MOD-7)
    • Flip Flops using FSM.
  • SHIFT REGISTERS & MEMORIES
    • SISO
    • PIPO
    • SIPO
    • PISO
    • Memory Design
    • RAM
    • ROM
  • MINOR PROJECTS
    • Design of ALU
    • Traffic Light Controller
    • Single way
    • Four way
    • Design of Shift Unit
    • Design of Comparator
    • Booth Multiplier
    • Wallance Tree MultiplierDesign of Shift Unit
  • HARDWARE INTERFACING
    • Introduction to FPGA.
    • Introduction to CPLD.
    • Brief Description of Hardware KIT.
    • Working on Physical FPGA & CPLD.
    • Interfacing of LED’s.
    • Keypad Scanner
  • BEHAVIORAL MODELING ADVANCED TOPICS
    • MEMORY DESIGN – RAM / ROM
    • CLOCK DIVIDER RTL
  • HARDWARE INTERFACING ADVANCED TOPICS
    • 7 Segment interfacing.
    • Counter on 7-Segment.
    • LCD Interfacing.
  • ADVANCE TOPICS
    • Test bench.
    • Delays in VHDL.
    • Generics & generic map.
    • Guarded block.
    • Overloading
    • Operator overloading.
    • Function overloading.
  • INDRODUCTION TO VERILOG HDL
    • Needs of VERILOG HDL.
    • Difference between Verilog HDL & VHDL.
    • Application of Verilog HDL
    • Market Need

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